Portable electrical equipment increasingly uses a single supply voltage of 5V or less, and reduced supply voltage designs need to use the complete power supply span, or rail to rail power supply, to have a usable dynamic range. FIG. 1A shows the diagram of a prior art rail to rail output DMOS amplifier. As shown, the amplifier 100 is a multi stage amplifier, with a high gain stage followed by an output driver stage. An input stage 101 receives input signals inputp and inputn and provides output signals a1 and ndrive. A high gain stage comprises a high side current mirror 102, an output biasing circuit 103 and a low side current source 104. The output driver stage comprises a high side PMOS driver 105 and a low side NMOS driver 106. The output biasing circuit 103 receives input currents from the low side current source 104 and the high side current mirror 102. In response to the input currents, the output bias block 103 sets the bias voltage pdrive for the high side driver 105 and ndrive the low side driver 106.
The high side current mirror 102 comprises high side current mirrors 1021 and 1022 which receive b1 and pdrive from the output biasing circuit 103 respectively, and are coupled to the power rail VDD. The low side current source 104 comprises low side current sources 1041 and 1042 which receive a1 and ndrive from the input stage 101 respectively, and are coupled to the power rail VSS. The high side PMOS driver 105's gate is controlled by pdrive, and its source is coupled to VDD. The low side NMOS driver 106's gate is controlled by ndrive, and its source is coupled to VSS. The output 107 of the amplifier is taken from the conjunction of the drains of drivers 105 and 106. The output swing is VDD to VSS, as shown in FIG. 1B. In other words, it's output is rail to rail.
The connection between the output driver stage and the preceding stage (e.g., the high gain stage in FIG. 1A) effects the performance of the preceding stage and hence the amplifier gain. In a typical MOS amplifier, the last gain stage (e.g., the high gain stage in FIG. 1A) will drive the gate of a MOS output driver, which may be a high side PMOS or a low side NMOS for amplifiers that can drive to one or both rails (e.g., the output driver stage in FIG. 1A). In the amplifier shown in FIG. 1A, the gate bias voltage of a driver is a gate to source voltage Vgs away from the power rails, and the headroom across the high gain stage current mirrors/sources is VDD−Vpdrive=Vgs_p on the high side, and Vndrive−VSS=Vgs_n on the low side. Thus, over process skew and temperatures on many amplifiers, the preceding stage current mirrors must stay in saturation with a headroom of just one Vgs, e.g., Vgs_p or Vgs_n in FIG. 1A.
The headroom, or the Vgs, can be as low as 0.4V at high operating temperatures and process skew. This limits the amount of degeneration overdrive and cascoding that can be used in implementing the biasing of the mirrors. This can directly effect their matching (amplifier offset) and also their output impedance (amplifier gain). The lower the gate to source voltage Vgs of the output driver, the more difficult it is to keep the gain of the preceding gain stage high. This is usually because the preceding stage has a high output impedance current mirror/source. As the voltage headroom across this drops, the current mirror/source can come out of saturation, resulting in a drop in the impedance at the output of the gain stage which lowers the amplifier gain. This is particularly the case for a two stage amplifier with one high gain stage followed by a drive stage.
Therefore, it would be desirable to provide a method and circuit to increase the drive voltage in the output driver. This will allow more headroom across the mirrors and allow better biasing and performance of the mirrors, enhancing the amplifier performance and robustness in a simple manner.